SERVER PLATFORM DEBUG HW ARCHITECT

Job Details.
Job Description.
Come and join a dynamic and challenging team within the Intel Data Center and AI Group (DCAI) focused on developing and supporting world class platforms and component building blocks aligned to roadmap and strategies.
Our mission is to enable breakthrough innovation for cloud computing in Intel's Data Platform Engineering and Architecture group (DPEA).
The Data Center Group Platform Architecture team is seeking an experienced, self-motivated candidate to fulfill the role of Server Platform Architect focusing on Platform Debug Infrastructure.
As a Platform Hardware Architect focusing on the debug Infrastructure (aka bare metal) across all Data Center Group Platforms, your multi segment responsibilities will include.
Lead or contribute to the development of new debug interfaces, use models and complete technical readiness for these technologies.
Contribute to or define future platform debug architecture concepts.
Comprehend production use models as well as requirements for HVM all in the effort of higher quality.
Provide deep analysis and recommendation in specific subsystem architecture areas in support of broader platform debug definition.
Support product business and planning teams to complete product feature freeze and final architecture definition.
Engage in customer discussions to obtain feedback on specific features or technologies.
Drive the platform architectural definition and document the full architecture in the Debug Platform Architecture Specification.
Support design engineering teams in product development phase as well as representing platform architecture issues exposed in design, validation, and test.
Qualifications.
Minimum Requirements.
You must possess the below minimum qualifications to be initially considered for this position.
The candidate must have a bachelor's in computer engineering, electrical engineering or related field.
7+ years of experience with.
Debug experience at platform level and/or component level, this could be software and/or hardware.
Debug tools in Lab/Production environments.
Technical domains such as SoC Architecture, Memory, RAS (reliability, accessibility, serviceability), and/or PCIe.
Advanced English level.
Must have unrestricted - permanent right to work in Mexico.
Preferred qualifications, Preferred qualifications are in addition to the minimum requirements and are considered a positive factor in identifying top candidates.
Master's degree with 6+ years of industry experience in Computer Engineering, Electrical Engineering or related field.
Experience with Intel XEON processor architecture focusing on DFx use cases including early break/patch, security levels etc.
Experience with server system architectures including closed chassis, open chassis, scale up, and scale out debug.
Experience with debug infrastructure utilized in the industry (JEDEC, IEEE, MIPI).
Security technologies such as authentication, cryptography, secure protocols, etc.
Platform/SoC architectures focusing on debug technologies such as At-Scale Debug, Direct Chassis DCI, ITP-XDP/Lauterbach, MIPI-PTI, JTAG, SMBus/I2C/I3C) as well as customer specific tools (Asset, Green Hill).
Requirements listed may be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Job Type.
Experienced Hire Shift.
Shift 1 (Mexico) Primary Location.
Mexico, Guadalajara Additional Locations.
Business group.
The Data Platforms Engineering and Architecture (DPEA) Group invents, designs & builds the world's most critical computing platforms which fuel Intel's most important business and solve the world's most fundamental problems.
DPEA enables that data center which is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.
Posting Statement.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
In certain circumstances the work model may change to accommodate business needs.
Intel provides reasonable accommodation to applicants and employees.
For more information on our Reasonable Accommodation process, please click here.
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